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1/12 l9826 april 2004 outputs current capability up to 450ma r on = 2.2 ? at t j = 25c parallel control inputs for outputs 1 and 2 spi control for outputs 1 to 8 reset function with reset signal at nres pin or undervoltage at v cc intrinsic output voltage clamping at typ. 50v overcurrent shutdown at outputs 3 to 8 short circuit current limitation and selective thermal shutdown at outputs 1 and 2 output status data available on the spi table 1. order codes description the l9826 is a octal low-side driver circuit, ded- icated for automotive applications. output voltage clamping is provided for flyback current recircula- tion, when inductive loads are driven. chip select and serial peripheral interface for outputs control and diagnostic data transfer. parallel control in- puts for two outputs. part number package l9826 so20 so20 (16+2+2) octal low-side driver for resistive and inductive loads with serial/parallel input control, ou tput protection and diagnostic block diagram ncs sdi clk sdo non1 out1 out2 out3 out4 out5 out6 out7 out8 gnd diag1 diag8 nres q1 ch1 diag1 + - ch7 diag7 q7 q1 q8 ch3 diag3 q3 + - ch4 ch5 ch6 ch2 non2 diag2 diag4 q4 diag5 q5 diag6 q6 q8 ch8 diag8 fault latch q2 reset shift register output latch spi interface r s latch / driver reset undervoltage reset 3 1 2 s r latch / driver q2 q3 q4 q5 q6 q7 diag2 diag3 diag4 diag5 diag6 diag7 v cc v cc v cc v cc v cc v cc v cc v dg i ol i ol v dg overtemperature detection gnd
l9826 2/12 pin function pin connections (top view) n pin description 1 out 6 output 6 2 out 1 output 1 3 nres asynchronous reset 4 ncs chip select (active low) 5 gnd device ground 6 gnd device ground 7 non1 control input 1 8 sdo serial data output 9 out 8 output 8 10 out 3 output 3 11 out 5 output 5 12 out 2 output 2 13 sdi serial data input 14 clk serial clock 15 gnd device ground 16 gnd device ground 17 non2 control input 2 18 v cc supply voltage 19 out 7 output 7 20 out 4 output 4 out6 out1 nres ncs gnd non1 gnd sdo out8 out2 sdi clk gnd gnd non2 vcc out7 out4 1 3 2 4 5 6 7 8 9 18 17 16 15 14 12 13 11 19 10 20 out3 out5 pincon_l9826
3/12 l9826 absolute maximum ratings for voltages and currents applied externally to the device notes: 1. all inputs are protected against esd according to mil 883c; tested with hbm at 2kv. it corresponds to a dissipated ener gy e 0,2mj. 2. transient pulses in accordance to din40839 part 1, 3 and iso 7637 part 1, 3. for currents determined within the device: 3. when operating the device with short circuit at more than 2 outputs at the same time, damage due to electrical overstress may occur. thermal data symbol parameter test condition min. typ. max. unit v cc supply voltage -0.3 7 v inputs and data lines (nonx, ncs, clk, sdi, nres) v in voltage (nonx, ncs, clk, sdi, nres) -0.3 7 v i in protection diodes current 1) t 1ms -20 20 ma outputs (out1 ... out8) v outc continuous output voltage -0.7 45 v i out output current 2) -2 1.0 a e outcl output clamp energy i out 150ma 10 mj symbol parameter test condition min. typ. max. unit outputs (out1 ... out8) i out output current (out1, out2) i lim a output current (out3 ... out8) i scb a i = 1-8 total average-current all outputs 3) t amb = 60c 2.0 a symbol parameter test condition min. typ. max. unit thermal shutdown t jsc thermal shutdown threshold 150 165 c thermal resistance r thja-one single output (junction ambient) 90 c/w r thja-all all outputs (junction ambient) 75 c/w r thj-pin junction to pin 18 c/w i outi
l9826 4/12 electrical characteristcs (4.5v v cc 5,5v; -40c t j 150c; unless otherwise specified) symbol parameter test condition min. typ. max. unit supply voltage i ccstb standby current without load (nres = low) 70 a i ccopm operating mode i out1 ... 8 = 500ma spi - clk = 3mhz ncs = low sdo no load 5ma ? i cc ? i cc during reverse output current i out = -2a 100 ma v ddres undervoltage reset reset of all registers and disable of all outputs 34v inputs (nonx. ncs, clk, sdi, nres) v inl low level -0.3 0.2v cc v v inh high level 0.7v cc v cc +0,3 v v hyst hysteresis voltage 0.85 v i in input current nonx, ncs, clk, sdi v in = v cc 10 a nres (v in = 0v) -10 a r in pullup resistance (nonx, ncs, clk, sdi) pulldown resistance (nres) 50 250 k ? c in input capacitance guaranteed by design 10 pf serial data outputs v sdoh high output level i sdo = -4ma v cc -0.4 v v sdol low output level i sdo = 3,2ma 0.4 v i sdol tristate leakage current ncs = high; 0v v sdo v cc -10 10 a c sdo output capacitance f sdo = 300khz, guaranteed by design 10 pf outputs out 1 ... 8 i outl1 - 8 leakage current outx = off; v outx = 25v; v cc = 5v 100 a i outl1 - 8 leakage current outx = off; v outx = 16v; v cc = 5v 100 a i outl1 - 8 leakage current outx = off; v outx = 16v; v cc = 1v 10 a v clp output clamp voltage 1ma i clp i outp ; i test = 10ma with correlation 45 62 v r dson on resistance out 1 ... 8 i out = 250ma; t j = +150c 3.0 ?
5/12 l9826 c out output capacitance v out = 16v; f = 1mhz guaranteed by design 300 pf outputs short circuit protection i sbc overcurrent shutoff threshold out3 ... out8 0.45 1.1 a i lim short circuit current limitation out1; out2 0.5 1.1 a t scb delay shutdown 0.2 3,0 12 s diagnostics v dg diagnostic threshold voltage 0.32v cc 0.4v c c v i ol open load detection sink current v out = v dg 20 100 a t df diagnostic detection filter time for output 1 & 2 on each diagnostic condition 15 50 s outputs timing t don1 turn on delay of out 1 and 2 non 1, 2 = 50% to v out = 0,9v bat ncs = 50% to v out = 0,9v bat (v bat = 16v, r l = 500 ? ) 5s t don2 turn on delay of out 3 to 8 ncs = 50% to v out = 0,9v bat (v bat = 16v, r l = 500 ? ) 10 s t doff turn off delay of out 1 to 8 ncs = 50% to v out = 0,1v bat non 1, 2 = 50% to v out = 0,1v bat (v bat = 16v, r l = 500 ? ) 10 s du on1/dt turn on voltage slew-rate for output 3 to 8; 90% to 30% of v bat ; r l = 500 ? ; v bat = 16v 0.7 3.5 v/s du on2/dt turn on voltage slew-rate for output 1 and 2; 90% to 30% of v bat ; r l = 500 ? ; v bat = 16v 210v/s du off1/dt turn off voltage slew-rate for output 1 to 8; 30% to 90% of v bat ; r l = 500 ? ; v bat = 16v 210v/s du off2/dt turn off voltage slew-rate for output 1 to 8; 30% to 80% of v bat ; r l = 500 ? ; v bat = 0.9 v clp 215v/s serial diagnostic link (load capacitor at sdo = 100pf) f clk clock frequency 50% duty cycle 3 mhz t clh minimum time clk = high 160 ns t cll minimum time clk = low 160 ns t pcld propagation delay clk to data at sdo valid 4,9v v cc 5,1v 100 ns t csdv ncs = low to data at sdo active 100 ns symbol parameter test condition min. typ. max. unit electrical characteristcs (continued)
l9826 6/12 functional description general the l9826 integrated circuit features 8 power low-side-driver outputs. data is transmitted to the device using the serial peripheral interface, spi protocol. outputs 1 and 2 can be controlled parallel or serial. the power outputs features voltage clamping function for flyback current recirculation and are protected against short cir- cuit to vbat. the diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 , overcurrent and ther- mal overload for outputs 1 and 2 in switch-on condition and 2) open load or short to gnd in switch-off condition for all outputs. the outputs status c an be read out via the serial interface. the chip internal reset is a or function of the external nres signal and internally generated undervoltage nres signal. output stages control each output is controlled with its latch and with common reset line, which enables all eight outputs. outputs 1 and 2 can be controlled also by its non1, non2 inputs. it allows pwm control independently on the spi. these inputs features internal pull-up resistors to assure t hat the outputs are switched off, when the inputs are open. the control data are transmitted via the sdi input, the timing of the serial interface is shown in fig. 1. the device is selected with low ncs signal and the input data are transferred into the 8 bit shift register at every falling clk edge. the rising edge of the ncs latches the new data from the shift register to the drivers. t sclch clk low before ncs low setup time clk to ncs change h/l 100 ns t hclcl clk change l/h after ncs = low 100 ns t scld sdi input setup time clk change h/l after sdi data valid 20 ns t hcld sdi input hold time sdi data hold after clk change h/l 20 ns t sclcl clk low before ncs high 150 ns t hclch clk high after ncs high 150 ns t pchdz ncs l/h to output data float 100 ns ncs pulse filter time multiple of 8 clk cycles inside ncs period symbol parameter test condition min. typ. max. unit electrical characteristcs (continued)
7/12 l9826 figure 1. timing of the serial interface. the spi register data are transferred to the output latc h at rising ncs edge. the digital filter between ncs and the output latch ensures that the data are transferred only after 8 clk cycles or multiple of 8 clk cycles since the last ncs falling edge. the ncs changes only at low clk. outputs control tables : figure 2. output control register structure outputs 1, 2: outputs 3 to 8: non1, 2 1001 spi-bit 1, 2 0 0 1 1 spi-bit 3 ... 8 0 1 output 1, 2 off on on on output 3 ... 8 off on ncs clk sdi sdo tsclch thclcl tclh tcll tsclcl thclch tcsdv tpcld tpchdz not defined d8 d1 tscld thcld d8 d7 d1 q2 q4 q6 q8 q1 q3 q5 q7 msb lsb control-bit output 7 control-bit output 5 control-bit output 3 control-bit output 1 control-bit output 8 control-bit output 6 control-bit output 4 control-bit output 2
l9826 8/12 power outputs characteristics for flyback current, outputs short ci rcuit protection and diagnostics for output currents flowing into the circuit the output voltage s are limited. the typical value of this voltage is 50v. this function allows that the flyback current of a inductive load recirculates into the circuit; the flyback energy is absorbed in the chip. output short circuit protection for outputs 3 to 8 (dedicated for loads without inrush current): when the output current exceeds the short circuit threshold, the corresponding output overload latch is set and the output is switched off immediately. output short circuit protection for outputs 1 and 2 (dedicat ed for loads with inrush current, as lamps): when the load current would exceed the short circuit limit value, the corresponding output goes in a current regulation mode. the output current is determi ned by the output characteristics and the output voltage depends on the load resistance. in this mode high power is dissipated in the output transistor and its temperature increases rap- idly. when the power transistor temperature exceeds the thermal shutdown threshold, the overload latch is set and the corresponding output switched off. for the load diagnostic in output off condition each output features a diagnostic current sink, typ 60a. diagnostics the output voltage at all outputs is compared wi th the diagnostic threshold, typ 0,38 v cc . outputs 1 and 2 features dedicated fault latches. the output st atus signal is filtered and latched. the fault latch- es are cleared during ncs low. the latch stores the status bit, so the first reading after the error occurred might be wrong. the second reading is right. diagnostic table for outputs 1 and 2 in parallel controlled mode: fault condition 1) "output short circuit to vbat" : th e output was switched on and the voltage at the output ex- ceeds the diagnostics threshold. the output operates in current regulation mode or has been switched off due to thermal shutdown. the status bit is low. fault condition 2) "open load" or "output short circuit to gnd" : the output is switched off and the voltage at the output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur- rent source, the load is interrupted. the diagnostic bit is low. for outputs 3 to 8 the output status signals, are fed directly to the spi register. diagnostic table for outputs 1 to 8 in spi controlled mode: output 1, 2 output-voltage status-bit output-mode off > dg-threshold high correct operation off < dg-threshold low fault condition 2) on < dg-threshold high correct operation on > dg-threshold low fault condition 1) output 1 ... 8 output-voltage status-bit output-mode off > dg-threshold high correct operation off < dg-threshold low fault condition 2) on < dg-threshold low correct operation on > dg-threshold high fault condition 1)
9/12 l9826 the fault condition 1) "output short circuit to vbat" : the output was switched on and the voltage at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the output has been switched off. the diagnostic bit is high. fault condition 2) "open load" or "output short circui t to gnd" is the same as of outputs 1 and 2. at the falling edge of ncs the output status data are transfe rred to the shift register. when nsc is low, data bits contained in the shift register are transferred to sdo output et every rising clk edge. figure 3. the pulse diagram to read the outputs status register figure 4. the structure of the outputs status register ncs clk sdi sdo msb lsb 654321 msb lsb 654321 diag2diag4 diag6 diag8 diag1diag3 diag5diag7 msb lsb diagnostic-bit output 7 diagnostic-bit output 5 diagnostic-bit output 3 diagnostic-bit output 1 diagnostic-bit output 8 diagnostic-bit output 6 diagnostic-bit output 4 diagnostic-bit output 2
l9826 10/12 application information the typical application diagram is shown in fig. 5. figure 5. typical application circuit diagram for the l9826 circuit. for higher current driving capability two outputs of the same kind can be paralleled. in this case the maximum flyback energy should not exceed the limit value for single output. the immunity of the circuit with respect to the transients at the output is verified during the characterization for test pulses 1, 2 and 3a, 3b, din40839 or iso7637 part 3. the test pulses are coupled to the outputs with 200pf series capacitor. all outputs withstand testpulses without damage. the correct function of the circuit with the test pulses coupled to the outputs is verified during the characteriza- tion for the typical application with r = 30 ? to 100 ? , l= 0 to 600mh loads. the test pulses are coupled to the outputs with 200pf series capacitor. ncs2 ... 7 clock sdi sdo nres cc v bat v r, l loads p l9826 l9826 voltage regulator ncs sdi clk sdo non1 out1 out2 out3 out4 out5 out6 out7 out8 gnd diag1 diag8 nres q1 ch1 diag1 + - ch7 diag7 q7 q1 q8 ch3 diag3 q3 + - ch4 ch5 ch6 ch2 non2 diag2 diag4 q4 diag5 q5 diag6 q6 q8 ch8 diag8 fault latch q2 reset shift register output latch spi interface r s latch / driver reset undervoltage reset 3 1 2 s r latch / driver q2 q3 q4 q5 q6 q7 diag2 diag3 diag4 diag5 diag6 diag7 v cc v cc v cc gnd v cc v cc v cc v cc v dg i ol i ol v dg overtemperature detection
11/12 l9826 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) ?d? dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so20 0016022 d
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